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FEATURES Low Distortion, High Output Current Amplifiers Operate from 12 V to 12 V Power Supplies, Ideal for High-Performance ADSL CPE, and xDSL Modems Low Power Operation 9 mA/Amp (Typ) Supply Current Digital (1-Bit) Power-Down Voltage Feedback Amplifiers Low Distortion Out-of-Band SFDR -80 dBc @ 100 kHz into 100 Line High Speed 175 MHz Bandwidth (-3 dB), G = +1 400 V/ s Slew Rate High Dynamic Range VOUT to within 1.2 V of Power Supply APPLICATIONS ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI, PCMCIA Modems, and Customer Premise Equipment (CPE) PRODUCT DESCRIPTION 8-Lead SOIC (R-8)
OUT1 -IN1 +IN1 -VS
1 2 3 4
DSL Line Driver with Power-Down AD8019
PIN CONFIGURATIONS 14-Lead TSSOP (RU-14)
+VS OUT2 -IN2 +IN2 NC OUT1 -IN1 +IN1 -VS PWDN NC
1 2 3 4 5 6 7
AD8019AR
8 7 6 5
AD8019ARU
14 13 12 11 10 9 8
NC +VS OUT2 -IN2 +IN2 NC DGND
NC = NO CONNECT
The AD8019 is a low cost xDSL line driver optimized to drive a minimum of 13 dBm into a 100 load while delivering outstanding distortion performance. The AD8019 is designed on a 24 V high-speed bipolar process enabling the use of 12 V power supplies or 12 V only. When operating from a single 12 V supply the highly efficient amplifier architecture can typically deliver 170 mA output current into low impedance loads through a 1:2 turns ratio transformer. Hybrid designs using 12 V supplies enable the use of a 1:1 turns ratio transformer, minimizing attenuation of the receive signal. The AD8019 typically draws 9 mA/ amplifier quiescent current. A 1-bit digital power down feature reduces the quiescent current to approximately 1.6 mA/amplifier. Figure 1 shows typical Out of Band SFDR performance under ADSL CPE (upstream) conditions. SFDR is measured while driving a 13 dBm ADSL DMT signal into a 100 line with 50 back termination. The AD8019 comes in thermally enhanced 8-lead SOIC and 14-lead TSSOP packages. The 8-lead SOIC is pin-compatible with the AD8017 12 V line driver.
10dB/DIV
-80dBc
132.5
137.5 FREQUENCY - kHz
142.5
Figure 1. Out-of-Band SFDR; VS = 12 V; 13 dBm Output Power into 200 , Upstream
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD8019-SPECIFICATIONS otherwise noted.)
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions
(@ 25 C, VS = 12 V, RL = 25
, RF = 500
, TMIN = -40 C, TMAX = +85 C, unless
Min Typ 35 180 75 6 35 50 450 5.5 40 Max Unit MHz MHz MHz MHz MHz MHz V/s ns ns
0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Out-of-Band SFDR MTPR Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage
G = +5 G = +1, VOUT < 0.4 V p-p, RL = 100 G = +2, VOUT < 0.4 V p-p, RL = 100 VOUT < 0.4 V p-p, RL = 100 G = +5, VOUT < 0.4 V p-p, RL = 100 VOUT = 4 V p-p Noninverting, VOUT = 4 V p-p Noninverting, VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 3 V p-p (Differential) 100 kHz, RL(DM) = 50 500 kHz, RL(DM) = 50 100 kHz, RL(DM) = 50 500 kHz, RL(DM) = 50 144 kHz-1.1 MHz, Differential R L = 70 25 kHz-138 kHz, Differential R L = 70 f = 100 kHz f = 100 kHz f = 1 MHz, G = +2
175 70
-78 -74 -85 -80 -80 -72 8 0.9 -80 8 10 1 2 80 80 10 0.5 +1 -0.5 -0.2 +0.1 74 10 0.2 20 23 12 17
dBc dBc dBc dBc dBc dBc nV/Hz pAHz dB mV mV mV mV dB dB M pF A A A A A A A A dB V V mA mA mA mA mA V dB ns ns V V A A
TMIN-TMAX Input Offset Voltage Match Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance +Input Bias Current TMIN-TMAX -Input Bias Current TMIN-TMAX +Input Bias Current Match TMIN-TMAX -Input Bias Current Match CMRR Input CM Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current1 POWER SUPPLY Supply Current/Amp TMIN-TMAX VCM = -4 V to +4 V TMIN-TMAX VOUT = 6 V p-p, RL = 25 TMIN-TMAX 72 72
-3 -4 -1.5 -1.8 -1.0 -1.5 -0.5 -0.8 71 2
+3 +4 +1.5 +1.8 +1.0 +1.5 +0.5 +0.8
RL = 25 SFDR -80 dBc into 25 at 100 kHz
-4.8 175
+4.8 200 400 9 0.8 10.5 14.5 2.0 6.0
Operating Range Power Supply Rejection Ratio LOGIC LEVELS tON tOFF PWDN = "1" Voltage PWDN = "0" Voltage PWDN = "1" Bias Current PWDN = "0" Bias Current
PWDN = 5 V TMIN-TMAX PWDN = 0 V Dual Supply VS = +1.0 V to -1.0 V VPWDN = 0 V to 3 V; VIN = 10 MHz, G = +5
4.0 65
68 120 80
1.8 220 -100
+VS 0.5
NOTES 1 This device is protected from overheating during a short-circuit by a thermal shutdown circuit. Specifications subject to change without notice.
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AD8019
(@ 25 C, VS =
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth
12 V, RL = 100
, RF = 500
, TMIN = -40 C, TMAX = +85 C, unless otherwise noted.)
Conditions G = +5 G = +1, VOUT < 0.4 V p-p G = +2, VOUT < 0.4 V p-p VOUT < 0.4 V p-p VOUT = 4 V p-p Noninverting, VOUT = 4 V p-p Noninverting, VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 16 V p-p (Differential) 100 kHz, RL(DM) = 200 500 kHz, RL(DM) = 200 100 kHz, RL(DM) = 200 500 kHz, RL(DM) = 200 144 kHz-500 kHz, Differential R L = 200 25 kHz-138 kHz, Differential R L = 200 f = 100 kHz f = 100 kHz f = 1 MHz, G = +2 Min Typ 35 180 75 5.5 50 400 5.5 40 Max Unit MHz MHz MHz MHz MHz V/s ns ns
175 70
0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Out-of-Band SFDR MTPR Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage
-80 -72 -85 -80 -80 -73 8 0.9 -85 5 10 1 2 92 90 10 0.5 -0.5 -0.2 +0.2 +0.1 76 +10 0.2 20 12 18
dBc dBc dBc dBc dBc dBc nV/Hz pAHz dB mV mV mV mV dB dB M pF A A A A A A A A dB V V mA mA mA mA mA V dB ns ns V V A A
TMIN-TMAX Input Offset Voltage Match Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance +Input Bias Current TMIN-TMAX -Input Bias Current TMIN-TMAX +Input Bias Current Match TMIN-TMAX -Input Bias Current Match CMRR Input CM Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current1 POWER SUPPLY Supply Current/Amp TMIN-TMAX VCM = -10 V to +10 V TMIN-TMAX VOUT = 18 V p-p, RL = 100 TMIN-TMAX 86
-3 -3.8 -1.5 -1.7 -1.0 -2.4 -1.0 -2.5 71 -10
+3 +3.8 +1.5 +1.7 +1.0 +2.4 +1.0 +2.5
RL = 100 SFDR -80 dBc into 100 at 100 kHz
-10.8 125
+10.8 170 800 9 10 11.5 1.75 12
Operating Range Power Supply Rejection Ratio LOGIC LEVELS tON tOFF PWDN = "1" Voltage PWDN = "0" Voltage PWDN = "1" Bias Current PWDN = "0" Bias Current
PWDN = High TMIN-TMAX PWDN = Low Dual Supply VS = +1.0 V to -1.0 V VPWDN = 0 V to 3 V; VIN = 10 MHz, G = +5
4.0 61
0.8 64 120 80
1.8 220 -100
+VS 0.5
NOTES 1 This device is protected from overheating during a short-circuit by a thermal shutdown circuit. Specifications subject to change without notice.
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AD8019
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V Internal Power Dissipation TSSOP-14 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W SOIC-8 Package3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at 85C 14-lead TSSOP package: JA = 90C/W. 3 Specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at 85C 8-lead SOIC package: JA = 100C/W.
The maximum power that can be safely dissipated by the AD8019 is limited by the associated rise in junction temperature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. The output stage of the AD8019 is designed for maximum load current capability. As a result, shorting the output to common can cause the AD8019 to source or sink 500 mA. To ensure proper operation, it is necessary to observe the maximum power derating curves. Direct connection of the output to either power supply rail can destroy the device.
2.5
MAXIMUM POWER DISSIPATION - W
2.0
TSSOP
1.5
1.0
SOIC
0.5
0 -40 -30 -20 -10 0 10 20 30 40 50 AMBIENT TEMPERATURE - C
60
70
80
Figure 2. Plot of Maximum Power Dissipation vs. Temperature for AD8019 for TJ = 150C
ORDERING GUIDE
Model AD8019ARU AD8019ARU-Reel AD8019ARU-EVAL AD8019AR AD8019AR-Reel AD8019AR-EVAL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 14-Lead TSSOP 14-Lead TSSOP Evaluation Board 8-Lead SOIC 8-Lead SOIC Evaluation Board
Package Option RU-14 RU-14 Reel ARU-EVAL R-8 R-8 Reel AR EVAL
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8019 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Typical Performance Characteristics-AD8019
124 499 RL VIN 49.9 +VS 0.1 F + 10 F + +VS VOUT +VIN 0.1 F 50 500 47 F 0.1 F 0.1 F + 10 F -VS -VIN 50 0.1 F 55 55 RL 500 +VO
-VO
-VS
TPC 1. Single-Ended Test Circuit; G = +5
TPC 4. Differential Test Circuit; G = +10
100 80 60 40
VOUT - mV
100 80 60 40
VOLTS - mV
20 0 -20 -40 -60 -80
20 0 -20 -40 -60 -80
-100 -100
0
100
200
300 TIME - ns
400
500
600
700
-100 -100
0
100
200
300
400
500
600
700
TIME - 100ns/DIV
TPC 2. 100 mV Step Response; G = +5, VS = 6 V, RL = 25 , Single-Ended
TPC 5. 100 mV Step Response; G = +5, VS = 12 V, RL = 100 , Single-Ended
4 3 2
VOUT - Volts VOUT - Volts
4 3 2 1 0 -1 -2 -3 -4 -100
1 0 -1 -2 -3 -4 -100
0
100
200
300 TIME - ns
400
500
600
700
0
100
200
300 TIME - ns
400
500
600
700
TPC 3. 4 V Step Response; G = +5, VS = 6 V, RL = 25 , Single-Ended
TPC 6. 4 V Step Response; G = +5, VS = 12 V, RL = 100 , Single-Ended
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AD8019
-20 -30 -40
-20 -30 -40
DISTORTION - dBc
DISTORTION - dBc
-50 -60 -70 -80 -90 2ND 3RD
-50 3RD -60 -70 -80 2ND -90
-100 0.01
0.1 FREQUENCY - MHz
1
5
-100 0.01
0.1 FREQUENCY - MHz
1
5
TPC 7. Distortion vs. Frequency; VS = 12 V, RL = 200 , Differential, VO = 16 V p-p
TPC 10. Distortion vs. Frequency; VS = 6 V, RL = 50 , Differential, VO = 3 V p-p
-30
-20 -30 -40
-40 -50 -60 -70 -80 -90 3RD HARMONIC 2ND HARMONIC
DISTORTION - dBc
DISTORTION - dBc
-50 -60 -70 2ND -80 -90 3RD
-100 50
75
100
125
150
175
200
-100
0
2
4
6
8
10
12
14
16
18
20
PEAK OUTPUT CURRENT - mA
DIFFERENTIAL OUTPUT VOLTAGE - V p-p
TPC 8. Distortion vs. Peak Output Current; VS = 6 V; RL = 10 ; f = 100 kHz; Single-Ended; Second Harmonic
TPC 11. Distortion vs. Output Voltage; f = 100 kHz, VS = 6 V, G = +10, RL = 50 , Differential
-20 -30 -40
DISTORTION - dBc
-10 -20 -30 DISTORTION - dBc -40 -50 2ND -60 -70 -80 -90 3RD
-50 -60 2ND HARMONIC -70 3RD HARMONIC -80 -90
-100 -110
-100 50
75
100
125
150
175
200
225
250
0
2
4
6
8
10
12
14
16
18
20
PEAK OUTPUT CURRENT - mA
DIFFERENTIAL OUTPUT VOLTAGE - V p-p
TPC 9. Distortion vs. Peak Output Current; VS = 12 V; RL = 25 ; f = 100 kHz; Single-Ended; Second Harmonic
TPC 12. Distortion vs. Output Voltage; f = 500 kHz, VS = 6 V, G = +10, RL = 50 , Differential
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-20 -30
11 8 5
OUTPUT VOLTAGE - dBV
-40
DISTORTION - dBc
2 -1 -4 -7 -10 -13
-50 -60 -70 -80 -90 2ND
3RD
-16 -19
-100 0 5 10 15 20 25 30 35 40 45 50 DIFFERENTIAL OUTPUT VOLTAGE - V p-p
1
10
100
1000
FREQUENCY - MHz
TPC 13. Distortion vs. Output Voltage; f = 100 kHz, VS = 12 V, G = +10, RL = 200 , Differential
TPC 16. Output Voltage vs. Frequency; VS = 12 V, RL = 100 ; G = +5
-10 -20 -30
DISTORTION - dBc
0 -10 -20 -30
-40 -50 -60 2ND -70 -80 -90 3RD
CMRR - dB
-40 -50 -60 909 -70 -80 -90 0.01 VIN 50 909 50 909 VOUT 50
909
-100 -110 0 5 10 15 20 25 30 35 40 45 50 DIFFERENTIAL OUTPUT VOLTAGE - V p-p
0.1
1 10 FREQUENCY - MHz
100
1000
TPC 14. Distortion vs. Output Voltage; f = 500 kHz, VS = 12 V, G = +10, RL = 200 , Differential
TPC 17. CMRR vs. Frequency; VS = 12 V, RL = 100
1.2 OUTPUT SATURATION VOLTAGE - Volts
11 8
1.1
5
1.0 0.9 0.8 0.7 VOH VOL -40 C VOH OUTPUT VOLTAGE - dBV 100 1000
2 -1 -4 -7 -10 -13 -16 -19 1 10 100 FREQUENCY - MHz 1000
+25 C
VOL +85 C VOH
0.6 0.5 0.1
VOL
1
10 LOAD CURRENT - mA
TPC 15. Output Saturation Voltage vs. Load; VS = 12 V, VS = 6 V
TPC 18. Output Voltage vs. Frequency; VS = 6 V, RL = 100 ; G = +5
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AD8019
-10 -20 -30 -40 -50 -60 -70 -80 -90 0.01 +PSRR -PSRR -20 -30 -40
CROSSTALK - dB
PSRR - dB
-50 -60 -70 -80 -90
0.1
1 10 FREQUENCY - MHz
100
1000
-100 0.01
0.1
1 10 FREQUENCY - MHz
100
1000
TPC 19. PSRR vs. Frequency; RL = 100
TPC 22. Crosstalk vs. Frequency, VS = 12 V, VS = 6 V; G = +2; VIN = 10 dBm
100
100
120 110 100 500 50 10 10 AOL 50 50 2k
270 225 50 50 180 135 PHASE - Degrees
VNOISE 10 +INOISE 10
90 80 70 GAIN - dB 60 50 40 30 20 10 0 -10 PHASE
VNOISE - nV Hz
INOISE - pA Hz
90 45
1 -INOISE
1
0 -45 1000
0.1 0.01
0.1
1 10 FREQUENCY - kHz
100
0.1 1000
-20 0.001
0.01
0.1 1 10 FREQUENCY - MHz
100
TPC 20. Noise vs. Frequency
TPC 23. Open-Loop Gain and Phase vs. Frequency
VIN
VIN
0.1%
2mV/DIV
2mV/DIV
0.1%
VOUT
VOUT
6.8pF 1.1k VIN 50 1.1k 50 50 VOUT
6.8pF 1.1k VIN 50 1.1k 50 50 VOUT
20ns/DIV
20ns/DIV
TPC 21. Settling Time 0.1%; VS = 12 V, RL = 100 , VOUT = 2 V p-p
TPC 24. Settling Time 0.1%; VS = 6 V, RL = 100 , VOUT = 2 V p-p
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1000
VOUT
100
VIN = 1V/DIV VOUT = 2V/DIV
OUTPUT IMPEDANCE -
10
0V
1
VIN
0.1
0.01
0V
0.001 0.01 0.1 1 10 FREQUENCY - MHz 100
-200
0
400
800 TIME - ns
1200
1600
TPC 25. Output Impedance vs. Frequency; VS = 12 V; VS = 6 V
TPC 28. Overload Recovery; VS = 6 V, G = +5, RL = 100
VOUT
VIN = 2V/DIV VOUT = 5V/DIV
VOUT
VIN = 1V/DIV VOUT = 2V/DIV
0V
0V
VIN
VIN 0V
0V -100 0 100 200 300 400 500 TIME - ns 600 700 800 900
-200
0
400
800 TIME - ns
1200
1600
TPC 26. Overload Recovery; VS = 12 V, G = +5, RL =100
TPC 29. Overload Recovery; VS = 6 V, G = +5, RL = 100
VOUT 0V
VIN = 2V/DIV VOUT = 5V/DIV
VIN 0V
-100
0
100
200
300 400 500 TIME - ns
600
700
800
900
TPC 27. Overload Recovery; VS = 12 V, G = +5, RL = 100
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AD8019
0 -10
-40 -30
-20
-50
13dBm
MTPR - dBc
SFDR - dBc
-30 -40 -50 11dBm -60 12dBm
13dBm
-60
11dBm 12dBm
-70
-80
-70 10dBm -80 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
-90 1.0
10dBm 1.1 1.2 1.3 1.4 TURNS RATIO - N 1.5 1.6 1.7
TURNS RATIO - N
TPC 30. MTPR vs. Turns Ratio; VS = 6 V, RL = 100 Line
TPC 32. SFDR vs. Turns Ratio; VS = 6 V, RL = 100 Line
-30
-50 -55 18dBm
-40
18dBm
-60 -65 -70 -75 -80 17dBm
MTPR - dBc
17dBm -60 16dBm -70 13dBm
SFDR - dBc
-50
-85 16dBm 13dBm 1.2 1.3 1.4 1.5 1.6 1.7
-80
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-90 1.0
1.1
TURNS RATIO - N
TURNS RATIO - N
TPC 31. MTPR vs. Turns Ratio; VS = 12 V, RL = 100 Line
TPC 33. SFDR vs. Turns Ratio; VS = 12 V, RL = 100 Line
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AD8019
GENERAL INFORMATION
+VS +VO RL -VO +VS
The AD8019 is a voltage feedback amplifier with high output current capability. As a voltage feedback amplifier, the AD8019 features lower current noise and more applications flexibility than current feedback designs. It is fabricated on Analog Devices' proprietary High Voltage eXtra Fast Complementary Bipolar Process (XFCB-HV), which enables the construction of PNP and NPN transistors with similar fTs in the 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features enable the construction of high-frequency, low-distortion amplifiers.
POWER-DOWN FEATURE
-VS
-VS
Figure 3. Simplified Differential Driver
A digitally programmable logic pin (PWDN) is available on the TSSOP-14 package. It allows the user to select between two operating conditions, full on and shutdown. The DGND pin is the logic reference. The threshold for the PWDN pin is typically 1.8 V above DGND. If the power-down feature is not being used, it is better to tie the DGND pin to the lowest potential that the AD8019 is tied to and place the PWDN pin at a potential at least 3 V higher than that of the DGND pin, but lower than the positive supply voltage.
POWER SUPPLY AND DECOUPLING
Remembering that each output device only dissipates for half the time gives a simple integral that computes the power for each device: (2 VO ) 1 (VS - VO ) x RL 2 The total supply power can then be computed as: PTOT = 4 (VS |VO | - VO ) x
2
1 + 2 IQ VS + POUT 2
The AD8019 can be powered with a good quality (i.e., low-noise) supply anywhere in the range from +12 V to 12 V. In order to optimize the ADSL upstream drive capability of 13 dBm and maintain the best Spurious Free Dynamic Range (SFDR), the AD8019 circuit should be powered with a well-regulated supply. Careful attention must be paid to decoupling the power supply. High quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCCs) should be used to minimize supply voltage ripple and power dissipation. In addition, 0.1 F MLCC decoupling capacitors should be located no more than 1/8 inch away from each of the power supply pins. A large, usually tantalum, 10 F to 47 F capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the AD8019 outputs.
POWER DISSIPATION
In this differential driver, VO is the voltage at the output of one amplifier, so 2 VO is the voltage across RL. RL is the total impedance seen by the differential driver, including back termination. Now, with two observations the integrals are easily evaluated. First, the integral of VO2 is simply the square of the rms value of VO. Second, the integral of | VO | is equal to the average rectified value of VO, sometimes called the mean average deviation, or MAD. It can be shown that for a DMT signal, the MAD value is equal to 0.8 times the rms value.
PTOT = 4 (0.8 VO rms VS - VO rms2 ) x 1 + 2 IQ VS + POUT RL
For the AD8019 operating on a single 12 V supply and delivering a total of 16 dBm (13 dBm to the line and 3 dBm to the matching network) into 17.3 (100 reflected back through a 1:1.7 transformer plus back termination), the dissipated power is: = 332 mW + 40 mW = 372 mW Using these calculations and a JA of 90C/W for the TSSOP package and 100C/W for the SOIC, Tables I-IV show junction temperature versus power delivered to the line for several supply voltages while operating with an ambient temperature of 85C. The shaded areas indicate operation at a junction temperature over the absolute maximum rating of 150C, and should be avoided.
Table I. Junction Temperature vs. Line Power and Operating Voltage for TSSOP
It is important to consider the total power dissipation of the AD8019 in order to properly size the heat sink area of an application. Figure 3 is a simple representation of a differential driver. With some simplifying assumptions we can estimate the total power dissipated in this circuit. If the output current is large compared to the quiescent current, computing the dissipation in the output devices and adding it to the quiescent power dissipation will give a close approximation of the total power dissipation in the package. A factor (~0.6-1) corrects for the slight error due to the Class A/B operation of the output stage. It can be estimated by subtracting the quiescent current in the output stage from the total quiescent current and ratioing that to the total quiescent current. For the AD8019, = 0.833.
PLINE, dBm 13 14 15 16 17 18
12 132 134 136 139 141 143
VSUPPLY 12.5 134 137 139 141 144 147
13 137 139 141 144 147 150
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Table II. Junction Temperature vs. Line Power and Operating Voltage for SOIC
VSUPPLY PLINE, dBm 13 14 15 16 17 18 12 137 140 142 145 147 150 12.5 140 142 145 148 150 153 13 143 145 148 151 154 157
energy and make the circuit less susceptible to RF interference. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended.
Evaluation Board
The AD8019 is available installed on an evaluation board for both package styles. Figures 8 and 9 show the schematics for the TSSOP evaluation board. The receiver circuit on these boards is typically unpopulated. Requesting samples of the AD8022AR, along with either of the AD8019 evaluation boards, will provide the capability to evaluate the AD8019 along with other Analog Devices products in a typical transceiver circuit. The evaluation circuits have been designed to replicate the CPE side analog transceiver hybrid circuits. The circuit mentioned above is designed using a 1-transformer transceiver topology including a line receiver, line driver, line matching network, an RJ11 jack for interfacing to line simulators, and differential inputs. AC-coupling capacitors of 0.1 F, C8, and C10, in combination with 10 k, resistors R24 and R25, will form a 1st order highpass pole at 160 Hz.
Transformer Selection
Table III. Junction Temperature vs. Line Power and Operating Voltage for TSSOP
VSUPPLY PLINE, dBm 13 14 15 16 +12 115 116 118 120 +13 118 119 121 123
Table IV. Junction Temperature vs. Line Power and Operating Voltage for SOIC
VSUPPLY PLINE, dBm 13 14 15 16 +12 118 120 122 124 +13 121 123 125 128
Thermal stitching, which connects the outer layers to the internal ground plane(s), can help to utilize the thermal mass of the PCB to draw heat away from the line driver and other active components.
LAYOUT CONSIDERATIONS
Customer premise ADSL requires the transmission of a 13 dBm (20 mW) DMT signal. The DMT signal has a crest factor of 5.3, requiring the line driver to provide peak line power of 560 mW. 560 mW peak line power translates into a 7.5 V peak voltage on a 100 telephone line. Assuming that the maximum low distortion output swing available from the AD8019 line driver on a 12 V supply is 20 V and taking into account the power lost due to the termination resistance, a step-up transformer with turns ratio of 1:1 is adequate for most applications. If the modem designer desires to transmit more than 13 dBm down the twisted pair, a higher turns ratio can be used for the transformer. This trade-off comes at the expense of higher power dissipation by the line driver as well as increased attenuation of the downstream signal that is received by the transceiver. In the simplified differential drive circuit shown in Figure 7, the AD8019 is coupled to the phone line through a step-up transformer with a 1:1 turns ratio. R1 and R2 are back termination or line matching resistors, each 50 (100 /(2 x 12)) where 100 is the approximate phone line impedance. A transformer reflects impedance from the line side to the IC side as a value inversely proportional to the square of the turns ratio. The total differential load for the AD8019, including the termination resistors, is 200 . Even under these conditions the AD8019 provides low distortion signals to within 2 V of the power supply rails. One must take care to minimize any capacitance present at the outputs of a line driver. The sources of such capacitance can include, but are not limited to EMI suppression capacitors, overvoltage protection devices and the transformers used in the hybrid. Transformers have two kinds of parasitic capacitances, distributed, or bulk capacitance, and interwinding capacitance. Distributed capacitance is a result of the capacitance created between each adjacent winding on a transformer. Interwinding capacitance is the capacitance that exists between the windings on the primary and secondary sides of the transformer. The existence of these capacitances is unavoidable, but in specifying
As is the case with all high-speed applications, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. Removing the ground plane on all layers from the areas near the input and output pins will reduce stray capacitance, particularly in the area of the inverting inputs. The signal routing should be short and direct in order to minimize parasitic inductance and capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize balanced performance. When running differential signals over a long distance, the traces on the PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated
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a transformer, one should do so in a way to minimize them in order to avoid operating the line driver in a potentially unstable environment. Limiting both distributed and interwinding capacitance to less than 20 pF each should be sufficient for most applications.
Stability Enhancements
from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line drivers such as single tone harmonic distortion or THD, two-tone Intermodulation Distortion (IMD) and third order intercept (IP3) become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms. A typical ADSL upstream DMT signal can contain as many as 27 carriers (subbands or tones) of QAM signals. Multi-Tone Power Ratio (MTPR) is the relative difference between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal) yielding an empty frequency bin. MTPR, sometimes referred to as the `empty bin test,' is typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third harmonic distortion components. Measurements of MTPR are typically made on the line side or secondary side of the transformer.
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Voltage feedback amplifiers may exhibit sensitivity to capacitance present at the inverting input. Parasitic capacitance, as small as several picofarads, in combination with the high-impedance of the input can create a pole that can dramatically decrease the phase margin of the amplifier. In the case of the AD8019, a compensation capacitor of 10 pF-20 pF in parallel with the feedback resistor will form a zero that can serve to cancel out the effects of the parasitic capacitance. Placing 100 in series with each of the noninverting inputs serves to isolate the inputs from each other and from any high frequency signals that may be coupled into the amplifier via the midsupply bias. It may also be necessary to configure the line driver as two separate, noninverting amplifiers rather than a single differential driver. When doing this, the two gain resistors can share an ac coupling capacitor of 0.1 F to minimize any dc errors. Adhering to previously mentioned layout techniques will also be of assistance in keeping the amplifier stable.
Receive Channel Considerations
0
A transformer used at the output of the differential line driver to step up the differential output voltage to the line has the inverse effect on signals received from the line. A voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid. The turns ratio of the transformer may also be dictated by the ability of the receive circuitry to resolve low-level signals in the noisy twisted pair telephone plant. While higher turns ratio transformers boost transmit signals to the appropriate level, they also effectively reduce the received signal to noise ratio due to the reduction in the received signal strength. Using a transformer with as low a turns ratio as possible will limit degradation of the received signal. The AD8022, a dual amplifier with typical RTI voltage noise of only 2.5 nV/Hz and a low supply current of 4 mA/amplifier is recommended for the receive channel.
DMT Modulation, Multi-Tone Power Ratio (MTPR) and Out-of-Band SFDR
POWER - dBm
-20
-40
-60
-80
0
100 50 FREQUENCY - kHz
150
Figure 4. DMT Waveform in the Frequency Domain
ADSL systems rely on Discrete Multi-Tone (or DMT) modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which are uniformly separated in frequency. A uniquely encoded, Quadrature Amplitude Modulation (QAM)like signal occurs at the center frequency of each subband or tone. See Figure 4 for an example of a DMT waveform in the frequency domain, and Figure 5 for a time domain waveform. Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s)
MTPR versus transformer turns ratio is depicted in TPCs 30 and 31 and covers a variety of line power ranging from 10 dBm to 18 dBm. As the turns ratio increases, the driver hybrid can deliver more undistorted power to the load due to the high output current capability of the AD8019. Significant degradation of MTPR will occur if the output of the driver swings to the rails, causing clipping at the DMT voltage peaks. Driving DMT signals to such extremes not only compromises "in band" MTPR, but will also produce spurs that exist outside of the frequency spectrum containing the transmitted signal. "Outof-band" spurious free dynamic range (SFDR) can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins. Compromising out-of-band SFDR is the equivalent of increasing near-end cross talk (NEXT). Regardless of terminology, maintaining out-of-band SFDR while reducing NEXT will improve the overall performance of the modems connected at either end of the twisted pair.
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Generating DMT Signals
At this time, DMT-modulated waveforms are not typically menu-selectable items contained within arbitrary waveform generators. Even using (AWG) software to generate DMT signals, AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D/A converters and output drivers used by AWG manufacturers. Similar to evaluating single-tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with Option 4, (12-/24-bit, TTL Digital Data Out), digitally coupled to Analog Devices' AD9754, a 14-bit TxDAC(R), buffered by an AD8002 amplifier configured as a differential driver. Note that the DMT waveforms, available on the Analog Devices website, www.analog.com, or similar. WFM files are needed to produce the necessary digital data required to drive the TxDAC from the optional TTL Digital Data output of the TEK AWG2021.
+12V
4 3 2
VOLTS
1 0 -1
-2
-3 -0.25 -0.20 -0.15 -0.10 -0.05 0 TIME - ms
0.05
0.10
0.15
0.20
Figure 5. DMT Signal in the Time Domain
0.1 F 0.1 F 10k 301 6V 0.1 F 0.1 F 50 301 10k 0.1 F 100 50 POUT 16dBm 100
10 F
R1 17.3
RL = 100
VIN
LINE POWER 13dBm
R2 17.3 1:1.7 TRANSFORMER
Figure 6. Recommended Application Circuit for Single +12 V Supply
+12V
0.1 F 0.1 F 10k 301 50 VIN 0.1 F 50 301 10k 0.1 F 100 -12V 0.1 F POUT 16dBm 100
10 F
R1 12.4
RL = 100
LINE POWER 13dBm
R2 12.4 1:1 TRANSFORMER 10 F
Figure 7. Recommended Application Circuit for 12 V Supply
TxDAC is a registered trademark of Analog Devices, Inc.
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R38 DNI TP10 13 C8 0.1 F 4 +V 3 -V AD8019 5 1 3 2 4 NC = 5,6 T1 C7 DNI C27 DNI TP23 TP24 PR2 TP2 R21 DNI TP8 R39 DNI R37 DNI C2 DNI TP4 R9 DNI 3 B JP5 TB1 3 C18 DNI C16 DNI R34 DNI C3 DNI TP5 R13 DNI R22 DNI *DNI : DO NOT INSTALL C4 10 F 25V + C21 0.1 F C20 0.1 F C17 DNI 2 A JP6 1 VCC-2 L1 BEAD R23 DNI TP9 B TB1 1 VCCIN L5 BEAD TP19 VCC C12 DNI TP25 TP26 C6 DNI TP1 P1 VEE R18 301 C22 DNI R36 DNI 1 R1 C13 0.1 F 2 R4 DNI R19 301 VEE A 11 -V U1 12 10 +V 13 VCC C1 DNI R33 DNI C10 0.1 F R14 100 R12 DNI VCC;8 VEE;4 1 3 U2 2 TP17 AD8022 5 AD8019 100 1WATT R3 DNI C29 DNI R20 DNI 8 9 7 C11 DNI DNI 10 R40 DNI U1 2 PR1 R35 DNI TP7 C9 DNI R8 100 TP6 A VCC R28 DNI R24 10k R32 100 VCC-2 C28 DNI C5 0.1 F R42 DNI R29 10k R41 DNI 1 JP7 3 AB 2 R2 50 1 2 3 4 5 6 78 TP11 C14 10 F 25V TB1 2
S5
R30 0
VCC
R11 50
3
B
JP4 A 2
1
P4 1
3
P4 2
B JP3 A 2
P4 3
1
VCC
R15 50
Figure 8. TSSOP Noninverting DSL Evaluation Board Schematic
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R6 DNI R5 DNI R7 DNI TP18 AD8022 U2 7 VCC;8 VEE;4 5 6 R10 DNI
S6
R31 0
+
S3
C26 0.1 F
C15 0.01 F U1 DECOUPLING TP12
C23 DNI U2 DECOUPLING
VCC
P3
3
VEE
P3
2
R16 5k TP3
P3
1
VCC-2
U1 DECOUPLING U2 DECOUPLING
R17 5k
S4
C19 0.1 F
AD8019
AD8019
VCC R25 VAL 9 NC4 1 JP1 A 2 B 3 C24 VAL U1 6 PWDN DGND NC1 8 1 NC2 NC3 7 14
AD8019
R26 VAL
R27 VAL
Figure 9. DSL Driver Input Control Circuit
Figure 11. TSSOP Evaluation Board Silkscreen Bottom
AGND AGND
2
Figure 10. TSSOP Evaluation Board Silkscreen Top
Figure 12. TSSOP Evaluation Board Power Plane
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Figure 13. Solder Mask Top
Figure 15. Ground Plane Bottom
Figure 14. Solder Mask Bottom
Figure 16. Assembly Top
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Figure 17. Ground Plane Top
Figure 18. Assembly Bottom
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Figure 19. Board Fabrication
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OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead TSSOP (RU-14)
C02551-1.5-4/01(0)
8 0 0.028 (0.70) 0.020 (0.50) 0.201 (5.10) 0.193 (4.90)
14
8
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 7
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8-Lead SOIC (R-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.102 (2.59) 0.094 (2.39) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
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PRINTED IN U.S.A.

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